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IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort? Static RAM
Functional Description
The IDT70V5388/78 provides a true synchronous
FourPort Static RAM interface. Registered inputs provide
minimal set-up and hold times on address, data, and all
critical control inputs. All internal registers are clocked on
the rising edge of the clock signal, however, the self-timed
internal write pulse is independent of the LOW to HIGH
transition of the clock signal and the duration of the R/ W
input signal. This is done in order to offer the fastest
possible cycle times and highest data throughput. At 200
MHz, the device supports a cycle time of 5 ns, and provides
a pipelined data output of 3.0 ns from clock edge to data
valid. Four ports operating at 200 MHz, each with a bus
width of 18 bits, results in a data throughput rate of nearly
14 Gbps.
As a true synchronous device, the IDT70V5388/78
provides the flexibility to clock each port independently: the
ports may run at different frequencies and/or out of synchro-
nization with each other. As a true FourPort device, the
IDT70V5388/78 is capable of performing simultaneous
reads from all ports on the same address location. Care
should be taken when attempting to write and read address
locations simultaneously: the timing diagrams depict the
critical parameter t CCS , which determines the amount of
time needed to ensure that the write has successfully been
completed and so valid data is available for output. Violation
A 16 /A 15(1)
Industrial and Commercial Temperature Ranges
of t CCS may produce indeterminate data for the read. Two or
more ports attempting to write the same address location
simultaneously will result in indeterminate data recorded at
that address.
Each port is equipped with dual chip enables, CE 0
and CE 1 . A HIGH on CE 0 or a LOW on CE 1 for one clock
cycle on any port will power down the internal circuitry on
that port in order to reduce static power consumption. The
multiple chip enables also allow easier banking of multiple
IDT70V5388/78s for depth expansion configurations. One
cycle is required with chip enables reasserted to reactivate
the outputs.
Depth and Width Expansion
The IDT70V5388/78 features dual chip enables
(refer to Truth Table I) in order to facilitate rapid and simple
depth expansion with no requirements for external logic.
Figure 4 illustrates how to control the various chip enables
in order to expand two devices in depth.
The IDT70V5388/78 can also be used in applica-
tions requiring expanded width, as indicated in Figure 3.
Through combining the control signals, the devices can be
grouped as necessary to accommodate applications re-
quiring 36-bits or wider.
IDT70V5388/78
CE 0
IDT70V5388/78
CE 0
Control Inputs
CE 1
V DD
Control Inputs
CE 1
V DD
IDT70V5388/78
CE 1
IDT70V5388/78
CE 1
Control Inputs
CE 0
Control Inputs
CE 0
UB , LB
R/ W ,
OE ,
CLK,
CNTLD ,
Figure 3. Depth and Width Expansion with IDT70V5388/78
NOTE:
1. A 16 is for IDT70V5388, A 15 is for IDT70V5378.
21
6.42
CNTRST ,
CNTINC
5649 drw 21
,
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